DocumentCode
1069783
Title
2K × 8 bit Hi-CMOS static RAM´s
Author
Minato, Osamu ; Masuhara, Toshiaki ; Sasaki, Toshio ; Nakamura, Hideaki ; Sakai, Yoshio ; Yasui, Tokumasa ; Uchibori, Kiyofumi
Author_Institution
Hitachi Central Research Laboratory, Tokyo, Japan
Volume
27
Issue
8
fYear
1980
fDate
8/1/1980 12:00:00 AM
Firstpage
1591
Lastpage
1595
Abstract
Two Hi-CMOS static RAM´s with 2K word by 8 bit organization have been developed. These RAM´s are fabricated with single polysilicon technology, which reduces processing costs. A novel J-FET powered static cell formed in the p well is used. The cell area is reduced to 80 percent that of the standard cell. Hi-CMOS well structure gives good immunity to alpha-particle-induced soft errors. These new RAM´s have an address access time of 74 ns, an operating power dissipation of 200 mW, and a standby dissipation of 25 µW.
Keywords
Application software; CMOS technology; Circuits; Computer peripherals; Costs; Flip-flops; MOS devices; Power supplies; Random access memory; Read-write memory;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1980.20075
Filename
1480868
Link To Document