Title :
A 1-Mbit full-wafer MOS RAM
Author :
Egawa, Yutaka ; Wada, Tsutome ; Ohmori, Yasuo ; Tsuda, Nobuo ; Masuda, Kiyoshi
Author_Institution :
Nippon Telegraph and Telephone Public Corporation, Tokyo, Japan
fDate :
8/1/1980 12:00:00 AM
Abstract :
A 3-in-diameter MOS RAM wafer with 1.256-Mbit net capacity has been designed. It is organized as two independent 32K word × 20 bit memories. Each 32K word memory comprises forty-six 20-kbit storage units, which, whether defective or not, are permanently connected to both buses and the power supply. Bit substitution and 32-word block substitution are used to counteract defects in storage units, and each wafer uses a combination of countermeasures against defects in its peripheral part. Fabricated RAM wafers showed 400-ns typical access time and 4.7-W power consumption at a 600-ns cycle time.
Keywords :
Costs; Energy consumption; Logic; Power supplies; Production; Random access memory; Read-write memory; Telegraphy; Telephony; Testing;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1980.20079
