Design Metrics Improvement for SRAMs Using Symmetric Dual- $k$ Spacer (SymD- $k$ ) FinFETs

Underlap FinFET devices, or trigate transistors, are considered to be the most favorable substitute to the conventional bulk device below 22-nm technology node. However, their application in circuit design requires specific attention because of the fin width quantization and increased parasitic. This paper proposes a double dielectric or dual- k spacers technology to enhance the electrostatic integrity of underlap FinFETs. For the first time, we investigate the circuit performance such as that of static RAMs (SRAMs), based on the proposed dual- k spacer FinFETs. The proposed structure enhances SRAMs performance in terms of robustness, access times, and the leakage power during all possible modes of operation. The hold, read, and write-margin increases by 8.7%, 9.4%, and 10.4%, respectively, as compared with conventional FinFET SRAM. Furthermore, the read and write access times reduces by 56% and 17.1%, respectively. Moreover, the standby leakage power is also reduced by ~ 73% compared with the conventional FinFET-based SRAM while occupying same bit-cell area.