Efficient CORDIC Algorithms and Architectures for Low Area and High Throughput Implementation

This paper presents two area-efficient algorithms and their architectures based on CORDIC. While the first algorithm eliminates ROM and requires only low-complexity barrel shifters, the second eliminates barrel shifters completely. As a consequence, both the algorithms consume approximately 50% area in comparison with other CORDIC designs. Further, the proposed algorithms are applicable to the entire range of angles. The FPGA implementations consume approximately 8% LUTs of a Xilinx Spartan XC2S200E device and have a slice-delay product of about 3. Convergence proofs for the algorithms are presented. Experimental comparisons with prior CORDIC designs confirm the efficacy of the proposed designs.