Design for Testability of CMOS Analog Sum-Product Error-Control Decoders

Author

Yiu, Mimi ; Winstead, Chris ; Gaudet, Vincent ; Schlegel, Christian

Author_Institution

IEEE, Shanghai

Volume

54

Issue

8

fYear

2007

Firstpage

675

Lastpage

679

Abstract

A built-in self-test (BIST) technique is presented for testing analog iterative decoders. Catastrophic circuit faults are detected by temporarily operating the analog soft gates in a digital mode. Self-testing operations are performed in the digital domain, thereby lowering the cost and complexity compared to alternative mixed-signal BIST approaches. A proof-of-concept CMOS integrated circuit realization of the BIST is also presented. BER measurements show that the added circuits do not interfere with the decoder´s performance during normal operation.

Keywords

CMOS analogue integrated circuits; built-in self test; design for testability; error correction codes; error statistics; iterative decoding; BER; CMOS analog sum-product error-control decoders; CMOS integrated circuit; Catastrophic circuit faults; built-in self-test technique; iterative decoders; Automatic testing; Built-in self-test; CMOS integrated circuits; Circuit faults; Circuit testing; Costs; Design for testability; Electrical fault detection; Fault detection; Iterative decoding; Error-control codes; analog decoding; built-in self-test (BIST); factor graphs; low-density parity check (LDPC) codes; message passing;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2007.898472

Filename

4277946