DocumentCode :
1074568
Title :
Simple and Accurate Models for Capacitance Considering Floating Metal Fill Insertion
Author :
Kim, Youngmin ; Petranovic, Dusan ; Sylvester, Dennis
Author_Institution :
QCT, Qualcomm Inc., San Diego, CA, USA
Volume :
17
Issue :
8
fYear :
2009
Firstpage :
1166
Lastpage :
1170
Abstract :
In this paper, we analyze and model the impact of floating dummy fill on the signal capacitance considering various parameters including signal dimensions, dummy shape and dimensions. Intra-layer dummy has its greatest impact on coupling capacitance while inter-layer dummy has larger impact on the ground capacitance component. Based on this analysis, we propose simple capacitance models (Cc for intra-layer dummy and Cg for inter-layer dummy). To consider realistic cases with both signals and metal fill in adjacent layers, we apply a weighting function approach to the Cg model. We verify this model using benchmark circuits and find that total net capacitance with floating fill can be extracted within ~1% of field solver results on average with total extraction runtime reductions of up to 40%. When evaluating the incremental capacitance due to fill alone, average error of the models range from 2%-15% across benchmarks and fill-related runtime overhead is reduced by 60%-88%.
Keywords :
capacitance; integrated circuit interconnections; integrated circuit metallisation; capacitance model; floating dummy fill; floating metal fill insertion; weighting function approach; Capacitance; design; integrated circuits (ICs); inter connects;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2009.2020392
Filename :
5075527
Link To Document :
بازگشت