DocumentCode :
107467
Title :
Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance
Author :
Yanbo Zhang ; Huilong Zhu ; Hao Wu ; Yongkui Zhang ; Zhiguo Zhao ; Jian Zhong ; Hong Yang ; Qingqing Liang ; Dahai Wang ; Junfeng Li ; Cheng Jia ; Jinbiao Liu ; Yuyin Zhao ; Chunlong Li ; Lingkuan Meng ; Peizhen Hong ; Junjie Li ; Qiang Xu ; Jianfeng Gao
Author_Institution :
Inst. of Microelectron., Beijing, China
Volume :
62
Issue :
5
fYear :
2015
fDate :
May-15
Firstpage :
1411
Lastpage :
1418
Abstract :
We present and demonstrate a self-aligned pocket well (SPW) structure used in planar bulk MOSFETs with a metal gate length of 25 nm and an effective channel length less than 20 nm. The SPW features a retrograde doping profile in vertical direction and a doping profile self-aligned with drain/extension in lateral direction. A novel process, called replacement spacer gate (RSG), is designed to avoid challenges in gate patterning and high-k metal gate filling. Planar bulk pMOSFETs, with SPW and halo doping, respectively, were simulated and fabricated adopting the RSG process. Due to its retrograde feature, the SPW can achieve low drain-induced barrier lowering (DIBL) along with low VT. Compared with halo doping with the same VT,sat at VDD = 0.8 V, despite no ION enhancement, the SPW reduces DIBL by 45% and enhances IEFF by 18%. Compared with halo doping with the same IOFF = 100 nA/μm at VDD = 0.8 V, the SPW structure reduces DIBL by 16%, enhances ION by 5%, and improves IEFF by 30%. In addition, with the self-aligned feature, the SPW does not deteriorate junction band-to-band tunneling (BTBT)
Keywords :
MOSFET; doping profiles; semiconductor doping; tunnelling; BTBT; DIBL; RSG process; SPW structure; drain-extension doping; gate patterning; halo doping; high-k metal gate filling; junction band-to-band tunneling; low drain-induced barrier lowering; planar bulk pMOSFET; replacement spacer gate; retrograde doping profile; self-aligned pocket well structure; short-channel effect; size 25 nm; voltage 0.8 V; Doping; Logic gates; MOSFET; Metals; Performance evaluation; Semiconductor device modeling; Semiconductor process modeling; Band-to-band tunneling (BTBT); drain-induced barrier lowering (DIBL); ground plane (GP); halo; pocket; short-channel effect (SCE); short-channel effect (SCE).;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2015.2410799
Filename :
7063232
Link To Document :
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