DocumentCode
1075256
Title
Comparison of various source-gate geometries for power MOSFET´s
Author
Hower, P.L. ; Geisler, M.J.
Author_Institution
Unitrode Corp., Watertown, MA
Volume
28
Issue
9
fYear
1981
fDate
9/1/1981 12:00:00 AM
Firstpage
1098
Lastpage
1101
Abstract
A simplified model is used to compare the influence of layout geometry on the parasitic drain resistance of a vertical DMOSFET. For each case, optimum dimensions are determined. For every geometry considered at least one-half of the total area is available for current conduction. The hexagon has been favored by some workers but slightly better results can be achieved with rectangles or with circles on hexagonal centers.
Keywords
Breakdown voltage; Doping; Electrodes; FETs; Geometry; MOSFET circuits; Power MOSFET; Research and development; Resistors; Solid modeling;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1981.20493
Filename
1481645
Link To Document