DocumentCode
1075585
Title
50 GHz static frequency divider in 130 nm CMOS
Author
Mo, Y. ; Skafidas, E. ; Evans, R. ; Mareels, I.
Author_Institution
Univ. of Melbourne, Melbourne
Volume
44
Issue
4
fYear
2008
Firstpage
285
Lastpage
286
Abstract
A novel circuit topology and design procedure to increase the operating frequency of current model logic (CML) static frequency dividers is proposed. The topology and design procedure are used to design a 50 GHz CML static frequency divider in 130 nm CMOS. The designed divider has a 20 GHz division bandwidth and consumes 11.7 mW power from a 1.5 V supply.
Keywords
CMOS integrated circuits; frequency dividers; integrated circuit design; network topology; CMOS; bandwidth 20 GHz; circuit design; circuit topology; frequency 50 GHz; power 11.7 mW; size 130 nm; static frequency divider; voltage 1.5 V;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20083638
Filename
4455411
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