Title :
A 300-MHz 64-b quad-issue CMOS RISC microprocessor
Author :
Benschneider, Bradley J. ; Black, Andrew J. ; Bowhill, William J. ; Britton, Sharon M. ; Dever, Dainel E. ; Donchin, Dale R. ; Dupcak, Robert J. ; Fromm, Richard M. ; Gowan, Mary K. ; Gronowski, Paul E. ; Kantrowitz, Michael ; Lamere, Marc E. ; Mehta, Sha
Author_Institution :
Digital Semiconductor, Hudson, MA, USA
fDate :
11/1/1995 12:00:00 AM
Abstract :
This 300 MHz quad-issue custom VLSI implementation of the Alpha architecture delivers 1200 MIPS (peak), 600 MFLOPS (peak), 341 SPECint92, and 512 SPECfp92. The 16.5 mm×18.1 mm die contains 9.3 M transistors and dissipates 50 W at 300 MHz. It is fabricated in a 3.3 V, four-layer metal, 0.5 μm, CMOS process. The upper metal layers (metal-3 and metal-4), primarily used for power, ground, and clock distribution. The chip supports 3.3 V/5.0 V interfaces and is packaged in a 499-pin ceramic IPGA. It contains an 8-kbyte instruction cache; an 8-kbyte, dual-ported, data cache; and a 96-kbyte, unified, second-level, 3-way set associative, fully pipelined, writeback cache. This paper describes the circuit and implementation techniques that were used to attain the 300 MHz operating frequency
Keywords :
CMOS digital integrated circuits; VLSI; cache storage; microprocessor chips; reduced instruction set computing; 0.5 micron; 1200 MIPS; 3-way set associative cache; 3.3 V; 300 MHz; 499-pin ceramic IPGA; 50 W; 600 MFLOPS; 64 bit; 8 kbyte; 96 kbyte; Alpha architecture; CMOS RISC microprocessor; custom VLSI implementation; dual-ported data cache; fully pipelined writeback cache; instruction cache; quad-issue microprocessor; CMOS process; Circuits; Clocks; Delay; Frequency; Microprocessors; Packaging; Pipelines; Reduced instruction set computing; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
