DocumentCode
1075890
Title
A 14-port 3.8-ns 116-word 64-b read-renaming register file
Author
Asato, Creigton
Author_Institution
HAL Computer Systems Inc., Campbell, CA, USA
Volume
30
Issue
11
fYear
1995
fDate
11/1/1995 12:00:00 AM
Firstpage
1254
Lastpage
1258
Abstract
A 116-word by 64-b register file for a 154 MHz four-issue superscalar processor renames read addresses and reads data in a single operation. A 10-port, 116-word tag comparison unit and a rename logic unit use static-bit-line techniques in the comparison logic. Pulsed-power sense amplifiers achieve a 3.8-ns read delay while dissipating 31% less power than a nonpulsed circuit
Keywords
CMOS digital integrated circuits; microprocessor chips; read-only storage; 0.4 micron; 154 MHz; 3.6 W; 3.8 ns; 64 bit; ROM; four-issue superscalar processor; pulsed-power sense amplifiers; read addresses; read-renaming register file; rename logic unit; static-bit-line techniques; tag comparison unit; CMOS process; Circuits; Clocks; Decoding; Logic arrays; Memory; Microprocessors; Pulse amplifiers; Registers; Trademarks;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.475713
Filename
475713
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