Title :
Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ±50 ps jitter
Author :
Novof, Iiay I. ; Austin, John ; Kelkar, Ram ; Strayer, Don ; Wyatt, Steve
Author_Institution :
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
fDate :
11/1/1995 12:00:00 AM
Abstract :
A fully integrated phase-locked loop (PLL) in a digital 0.5 μm CMOS technology is described. The PLL has a locking range of 15 to 240 MHz. The static phase error is less than 1100 ps with a peak-to-peak jitter of ±50 ps at a 100 MHz output frequency. The PLL has a resistorless architecture achieved by the implementation of feedforward current injection into the current controlled oscillator
Keywords :
CMOS integrated circuits; feedforward; jitter; mixed analogue-digital integrated circuits; phase locked loops; 0.5 micron; 15 to 240 MHz; ASIC; CMOS phase-locked loop; current controlled oscillator; feedforward current injection; fully integrated PLL; jitter; locking range; resistorless architecture; static phase error; Application specific integrated circuits; Charge pumps; Clocks; Filters; Frequency conversion; Frequency synchronization; Frequency synthesizers; Jitter; Output feedback; Phase locked loops;
Journal_Title :
Solid-State Circuits, IEEE Journal of
