Performance Analysis of 60-nm Gate-Length III–V InGaAs HEMTs: Simulations Versus Experiments

An analysis of recent experimental data for high-performance In_0.7Ga_0.3As high electron mobility transistors (HEMTs) for logic applications is presented. By using a fully quantum mechanical ballistic model, we simulate In_0.7Ga_0.3As HEMTs with gate lengths of L_G = 60, 85, and 135 nm and compare the result to the measured IV characteristics, including drain-induced barrier lowering, subthreshold swing, and threshold voltage variation with gate insulator (wide-bandgap barrier layer) thickness, as well as on-current performance. To first order, devices with three different oxide thicknesses and channel lengths can all be described by a ballistic model for the channel with appropriate values of parasitic series resistance. For high gate and drain voltages ( V_GS-V_T=0.5 V and V_DS=0.5 V), however, the ballistic simulations consistently overestimate the measured on-current (a sign of higher transconductance), and they do not show the experimentally observed decrease in on-current with increasing gate length. With no parasitic series resistance at all, the simulated on-current of the L_G = 60 nm device is about twice the measured current. According to the simulation, the estimated ballistic carrier injection velocity for this device is about 2.7 times 10⁷cm/s. Because of the importance of the semiconductor capacitance, the simulated gate capacitance is about 2.5 times less than the insulator/barrier capacitance. Possible causes of the transconductance degradation observed experimentally under high gate voltages in these devices are also explored. In addition to a possible gate-voltage-dependent scattering mechanism, the limited ability of the source to supply carriers to the channel and the effect of nonparabolicity are likely to play a role. The drop in the on-current at higher gate biases with increasing gate length, is an indication that the devices operate below th- e ballistic limit.