Title :
Clock buffer chip with multiple target automatic skew compensation
Author :
Watson, Richard B., Jr. ; Iknaian, Russell B.
Author_Institution :
Digital Semicond. Div., Digital Equipment Corp., Hudson, MA, USA
fDate :
11/1/1995 12:00:00 AM
Abstract :
This paper describes the application of a digital delay locked loop that compensates for variable delays on the clock chip, printed circuit board clock traces, and the clock systems on multiple ASICs. For a computer system consisting of nine PC boards (“modules”) plugged into a back plane with two clock chips per board and six ASICs per clock chip, a locking range of 25-150 MHz was achieved with a maximum skew in the system of less than 1 ns
Keywords :
CMOS digital integrated circuits; buffer circuits; compensation; delay circuits; timing circuits; 25 to 150 MHz; clock buffer chip; digital delay locked loop; multiple target automatic skew compensation; variable delay compensation; Application software; Application specific integrated circuits; Clocks; Control systems; Delay; Electromagnetic compatibility; Frequency; Printed circuits; Signal design; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
