A 1-Gb DRAM for file applications

Author

Sugibayashi, Tadahiko ; Naritake, Isao ; Utsugi, Satoshi ; Shibahara, Kentaro ; Oikawa, Ryuichi ; Mori, Hidemitsu ; Iwao, Shouichi ; Murotani, Tatsunori ; Koyama, Kuniaki ; Fukuzawa, Shinichi ; Itani, Toshiro ; Kasama, Kunihiko ; Okuda, Takashi ; Ohya, Sh

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan

Volume

30

Issue

11

fYear

1995

fDate

11/1/1995 12:00:00 AM

Firstpage

1277

Lastpage

1280

Abstract

A time-shared offset-canceling sensing scheme, a defective word-line Hi-Z standby scheme, and a flexible multimacro architecture have been developed for 1-Gb DRAM. These circuit technologies have been applied to a 1-Gb DRAM for file applications employing 0.25 μm CMOS process technology, a diagonal bit-line cell, and a two-stage pipeline circuit technique. In this DRAM, a 30% chip size reduction and a 400-MB/s data transfer rate have been achieved. A 100% improvement in yield has been estimated by Monte-Carlo simulation. The 1-Gb DRAM die size is 936 mm². The cell size is 0.54 μm². The operating current is 58 mA at 2 V and 100 MHz

Keywords

CMOS memory circuits; DRAM chips; pipeline processing; 0.25 micron; 1 Gbit; 100 MHz; 2 V; 400 MB/s; 68 mA; CMOS process; defective word-line Hi-Z standby scheme; diagonal bit-line cell; file applications; flexible multimacro architecture; gigabit DRAM; time-shared offset-canceling sensing scheme; two-stage pipeline circuit technique; CMOS process; CMOS technology; Circuit noise; Costs; Pipelines; Power dissipation; Random access memory; System performance; Threshold voltage; Yield estimation;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.475716

Filename

475716