Title :
VIB-1 scaling limitations of P channel devices in a CMOS technology
fDate :
10/1/1981 12:00:00 AM
Keywords :
CMOS technology; Circuit optimization; Circuit simulation; Electrons; Instruments; Integrated circuit modeling; Laboratories; Power dissipation; Very large scale integration; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1981.20590
