Design Methodology and Protection Strategy for ESD-CDM Robust Digital System Design in 90-nm and 130-nm Technologies

Author

Chen, Tze Wee ; Ito, Choshu ; Loh, William ; Wang, Wei ; Doddapaneni, Kalyan ; Mitra, Subhasish ; Dutton, Robert W.

Author_Institution

Dept. of Electr. Eng., Stanford Univ., Stanford, CA

Volume

56

Issue

2

fYear

2009

Firstpage

275

Lastpage

283

Abstract

A design methodology and protection strategy for ESD charged-device-model (CDM) robust digital systems is presented using a scalable postbreakdown transistor macromodel for 90- and 130-nm technologies. The macromodel was implemented in a design tool to aid reliable chip design and used to predict function failure in three different system-on-chip design examples. Simulations agree well with failure analysis observations, verifying the validity of the macromodel. A ldquocorrect-by-constructionrdquo protection strategy for overcoming induced ESD-CDM events is also proposed. No ESD-CDM-related function failures are observed for product chips protected with this strategy.

Keywords

digital integrated circuits; electrostatic discharge; integrated circuit design; microprocessor chips; system-on-chip; ESD charged-device-model; ESD-CDM robust digital system design; chip design; correct-by-construction protection strategy; design methodology; design tool; size 130 nm; size 90 nm; system-on-chip design; Circuit simulation; Design methodology; Digital systems; Electric breakdown; Electrostatic discharge; Indium tin oxide; Integrated circuit technology; Large scale integration; Protection; Robustness; Chip-level function failure prediction; ESD-charged device model (CDM); inductive coupling; postbreakdown transistor macromodel;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2008.2010586

Filename

4757246