Title :
An 8–11 Gb/s Reference-Less Bang-Bang CDR Enabled by “Phase Reset”
Author :
Shivnaraine, Ravi ; Jalali, Mohammad Sadegh ; Sheikholeslami, Ali ; Kibune, Masaya ; Tamura, H.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Abstract :
This paper embeds a “phase-reset” scheme into a bang-bang clock and data recovery (CDR) to periodically realign the clock phase to the data rising edge using a gated-VCO. This reduces both the CDR lock time and bit errors during pull-in, while increasing the CDR capture range. The CDR is fabricated in 65-nm CMOS, operates at 8-11 Gb/s, and demonstrates a 9 × increase in capture range. The CDR consumes 84 mW during lock, and 48 mW in steady state.
Keywords :
CMOS integrated circuits; clock and data recovery circuits; voltage-controlled oscillators; CDR lock; CMOS technology; bang-bang clock and data recovery; bit rate 8 Gbit/s to 11 Gbit/s; gated VCO; phase reset scheme; power 48 mW; power 84 mW; size 65 nm; Calibration; Clocks; Delays; Detectors; Frequency control; Voltage control; Voltage-controlled oscillators; Burst-Mode CDR; Clock and data recovery; Cycle-slipping; Gated VCO;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2014.2304668
