DocumentCode
1076759
Title
The reduction of emitter-collector shorts in a high-speed all-implanted bipolar technology
Author
Parrillo, Louis C. ; Payne, Richard S. ; Seidel, Tom E. ; Robinson, McDonald ; Reutlinger, Geirge W. ; Post, David E. ; Field, Richard L., Jr.
Author_Institution
Bell Laboratories, Murray Hill, NJ
Volume
28
Issue
12
fYear
1981
fDate
12/1/1981 12:00:00 AM
Firstpage
1508
Lastpage
1514
Abstract
One of the main yield limiting mechanisms in the fabrication of shallow-junction bipolar integrated circuits is emitter-to-collector (
) leakage. This paper describes the progress made in reducing the
leakage defect density in an all-implanted integrated circuit technology, which features emitters approximately 0.5 µm deep and bases approximately 0.3 µm wide. Tile median
short density was reduced from approximately 2 × 104to approximately 200/cm2of active emitter area in the course of this study. The processing changes that were adopted to reduce or eliminate the fatal defects include the use of both very low and very high temperature oxidation conditions to eliminate oxidation induced stacking faults (OSF\´s). A new epitaxial growth technique has reduced the slip dislocation density by more than an order of magnitude. The extended misfit dislocation arrays have been eliminated in both the collector contact and isolation diffusions by reducing the dopant concentrations in each region. Further, dislocation networks arising from buried layer and emitter regions, have been eliminated by limiting the oxygen concentration in their respective drive-in steps.
) leakage. This paper describes the progress made in reducing the
leakage defect density in an all-implanted integrated circuit technology, which features emitters approximately 0.5 µm deep and bases approximately 0.3 µm wide. Tile median
short density was reduced from approximately 2 × 104to approximately 200/cm2of active emitter area in the course of this study. The processing changes that were adopted to reduce or eliminate the fatal defects include the use of both very low and very high temperature oxidation conditions to eliminate oxidation induced stacking faults (OSF\´s). A new epitaxial growth technique has reduced the slip dislocation density by more than an order of magnitude. The extended misfit dislocation arrays have been eliminated in both the collector contact and isolation diffusions by reducing the dopant concentrations in each region. Further, dislocation networks arising from buried layer and emitter regions, have been eliminated by limiting the oxygen concentration in their respective drive-in steps.Keywords
Bipolar integrated circuits; Circuit faults; Epitaxial growth; Fabrication; Integrated circuit technology; Integrated circuit yield; Oxidation; Stacking; Temperature; Tiles;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1981.20638
Filename
1481790
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