A 0.5-to-3 GHz Software-Defined Radio Receiver Using Discrete-Time RF Signal Processing

A software-defined radio (SDR) wireless receiver leveraging discrete-time (DT) RF signal processing is introduced. The proposed DT signal processor, which applies switched capacitor techniques to radio frequencies, achieves harmonic rejection, image rejection, and frequency translation simultaneously. A frequency tunable high-Q 2nd-order bandpass input impedance is synthesized by the DT RF signal processor, which enhances the front-end interference rejection and frequency selectivity. A proof-of-concept SDR receiver prototype, including a 65 nm LP CMOS chip and a custom designed board, is presented. The highly programmable chip allows independent control of individual block parameters and bias operating points for optimum performance under various signal scenarios. The 0.5-to-3 GHz SDR receiver achieves out-of-band IIP3 > 11 dBm, IIP2 > 46 dBm, uncalibrated 3rd and 5th order harmonic rejection exceeding 46 dB and 51 dB, respectively, and can handle up to -5 dBm blockers with less than 5 dB degradation in signal-to-noise ratio (SNR) when the blocker offset frequency is 10 times the signal bandwidth irrespective of the center frequency.