Title :
Radiation-hard design for SOI MOS inverters
Author :
Francis, P. ; Michel, C. ; Flandre, D. ; Colinge, J.P.
Author_Institution :
Univ. Catholique de Louvain, Belgium
fDate :
4/1/1994 12:00:00 AM
Abstract :
The total-dose hardness of MOS integrated circuits is usually improved by increasing the hardness of the individual transistors. In this paper, we propose circuit design techniques that can further decrease the sensitivity of cells to radiation dose. This concept is applied to simple cells (inverters) produced in both thin-film SOI and gate-all-around technologies
Keywords :
CMOS integrated circuits; integrated logic circuits; logic gates; radiation hardening (electronics); semiconductor-insulator boundaries; silicon; SOI MOS inverters; Si-SiO2; Si-on-insulator; circuit design; gate-all-around technologies; radiation hard; thin-film; total-dose hardness; Circuit synthesis; Degradation; Integrated circuit technology; Inverters; MOS integrated circuits; MOSFETs; Microprocessors; Radiation hardening; Thin film circuits; Threshold voltage;
Journal_Title :
Nuclear Science, IEEE Transactions on
