DocumentCode
107743
Title
Space Vector Pulse Width Modulation for Three-Level NPC-VSI
Author
Betanzos, J.D. ; Rodriguez, Jeffrey J. ; Peralta, E.
Author_Institution
Inst. Politec. Nac., Mexico City, Mexico
Volume
11
Issue
2
fYear
2013
fDate
Mar-13
Firstpage
759
Lastpage
767
Abstract
This work addresses the design and experimental validation of a three-level Neutral-Point Clamped (NPC) inverter. A Space-Vector Modulation (SVM) algorithm which simplifies the space-vector diagram of a three-level inverter so that it can be used with a two-level inverter is developed. The dwell times are calculated on the simplification process in the same way as for a conventional two-level SVM method. Experimental results that validate the SVM algorithm developed to control the three-level NPC are presented. The SVM algorithm is programmed on a Freescale DSP56F8037 development system.
Keywords
PWM invertors; Freescale DSP56F8037 development system; SVM method; dwell times; neutral-point clamped inverter; simplification process; space vector pulse width modulation; space-vector diagram; three-level NPC-VSI; two-level inverter; Insulated gate bipolar transistors; Inverters; Pulse width modulation; Silicon; Support vector machines; Vectors; Three-level inverter; space-vector pulse width modulation;
fLanguage
English
Journal_Title
Latin America Transactions, IEEE (Revista IEEE America Latina)
Publisher
ieee
ISSN
1548-0992
Type
jour
DOI
10.1109/TLA.2013.6533965
Filename
6533965
Link To Document