Title :
Threshold voltage margin of normally-off GaAs MESFET in DCFL circuit
Author :
Ino, M. ; Kurumada, K. ; Ohmori, M.
Author_Institution :
Nippon Telegraph and Telephone Public Corporation, Tokyo, Japan
fDate :
6/1/1981 12:00:00 AM
Abstract :
The margin of threshold voltage (VT) for GaAs normally-off MESFET DCFL´s was numerically analyzed applying the equivalent inverter circuit model. The results show that the optimum (VT) is 0.3 V. Quantitative relation between the margin and delay time is obtained as a function of (VT). At (VT) = 0.3 V, the margin is 0.28 V with tpdless than 100 ps for 0.5 µm gate length.
Keywords :
Circuit simulation; Delay effects; Doping; Electron mobility; Gallium arsenide; Inverters; MESFET circuits; Parasitic capacitance; Semiconductor process modeling; Threshold voltage;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/EDL.1981.25375
