Low-roundoff-noise limit-cycle-free implementation of recursive transfer functions on a fixed-point digital signal processor

A method is presented for realizing recursive digital transfer functions on a fixed-point digital signal processor. The method is based on the parallel connection of L∞-norm scaled first- and second-order state-space structures. Magnitude truncation of the state update equations is employed to render the realization free of both overflow oscillations and constant-input limit cycles. The roundoff noise and coefficient sensitivity of the realization are also near minimum, giving a realization with outstanding performance in terms of all finite wordlength effects. An implementation on the DSP56000 family of digital signal processors demonstrates that the realization is efficient enough to achieve high sample rates