• DocumentCode
    1077622
  • Title

    Timing-Aware Multiple-Delay-Fault Diagnosis

  • Author

    Mehta, V.J. ; Marek-Sadowska, M. ; Kun-Han Tsai ; Rajski, J.

  • Author_Institution
    Design For Test Methodology Group, NVIDIA Corp., Santa Clara, CA
  • Volume
    28
  • Issue
    2
  • fYear
    2009
  • Firstpage
    245
  • Lastpage
    258
  • Abstract
    With feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design timing failures. It is essential that those errors be correctly and quickly diagnosed. In this paper, we analyze the multiple-delay-fault diagnosis problem and propose a novel approach to solve it. We enhance the diagnostic resolution by processing failure logs at various slower-than-nominal clock frequencies. We evaluate the utility of n-detection and timing-aware automatic-test-pattern-generated (ATPG) sets. Experimental results show that using timing-aware ATPG sets yields better diagnostic resolution and results in better delay-defect-size estimations compared to n -detection ATPG sets. We experimentally determined our diagnosis algorithm´s sensitivity to delay variations.
  • Keywords
    automatic test pattern generation; delay circuits; fault diagnosis; timing circuits; automatic-test-pattern-generated sets; delay-defect-size estimations; diagnostic resolution; failure logs; n-detection; slower-than-nominal clock frequencies; timing-aware multiple-delay-fault diagnosis; Automatic test pattern generation; Circuit faults; Delay estimation; Fault diagnosis; Logic; Manufacturing; Production; Silicon; Testing; Timing; Automatic test pattern generated (ATPG); delay testing; diagnosis; fault diagnosis; silicon debug; testing; timing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2008.2009164
  • Filename
    4757344