DocumentCode :
1077951
Title :
A Josephson technology system level experiment
Author :
Ketchen, M.B. ; van der Hoeven, B.J. ; Matisoo, J. ; Greiner, J.H. ; Herrell, D.J. ; Wang, R.H. ; Guernsey, R.W. ; Anderson, C.J. ; Arnett, P.C. ; Bermon, S. ; Bickford, H.R. ; Bright, A.A. ; Geldermans, P. ; Gheewala, T.R. ; Grebe, K.R. ; Jones, H.C. ; K
Author_Institution :
IBM T. J. Watson Research Center, Yorktown Heights, New York
Volume :
2
Issue :
10
fYear :
1981
fDate :
10/1/1981 12:00:00 AM
Firstpage :
262
Lastpage :
265
Abstract :
This letter describes the first system level test vehicle in Josephson technology. The experiment consists of four circuit chips assembled on two cards in a high density, 3-dimensional, card-on-board package. A data path, which is representative of a critical path of a future prototype processor, was successfully operated with a minimum cycle time of 3.7ns. The path simulates a jump control sequence and a cache access in each machine cycle. This experiment incorporates the essential components of the logic, power and package portions of a Josephson technology prototype.
Keywords :
Adaptive arrays; Assembly; Circuits; Magnetic flux; Packaging machines; Power cables; Prototypes; Silicon; Superconducting transmission lines; Wiring;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/EDL.1981.25426
Filename :
1481910
Link To Document :
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