Title :
Explaining Dynamic Cache Partitioning Speed Ups
Author :
Moreto, Miquel ; Cazorla, Francisco J. ; Ramirez, Alex ; Valero, Mateo
Author_Institution :
Univ. Politecnica de Catalunya, Barcelona
Abstract :
Cache partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, these new policies present different behaviors depending on the applications that are running in the architecture. In this paper, we introduce some metrics that characterize applications and allow us to give a clear and simple model to explain final throughput speed ups.
Keywords :
cache storage; microprocessor chips; chip multiprocessing; dynamic cache partitioning; shared cache levels; Computer architecture; Counting circuits; Parallel processing; Process design; Resource management; Streaming media; Surface-mount technology; Throughput; Uninterruptible power systems; Yarn; B Hardware; B.3 Memory Structures; B.3.2 Design Styles; B.3.2.b Cache memories; B.3.3 Performance Analysis and Design Aids; C Computer Systems Organization; C.1 Processor Architectures; C.1.4 Parallel Architectures; C.1.4.e Multi-core/single-chip multiprocessors; C.1.5 Micro-architecture implementation considerations; C.1.5.e Memory hierarchy; C.4 Performance of Systems; C.4.d Modeling techniques;
Journal_Title :
Computer Architecture Letters
DOI :
10.1109/L-CA.2007.3
