Delay and Energy Analysis of SEU and SET-Tolerant Pipeline Latches and Flip-Flops

In the presence of radiation, particle strikes can cause temporary signal errors in ICs. Particle strikes that directly affect memory are known as single event upsets (SEUs), while strikes that affect combinational logic and spread to memory are called single event transients (SETs). This paper focuses on SEU and SET-tolerant approaches to constructing pipeline latches and flip-flops. Level-sensitive latches, edge-triggered master-slave flip-flops, and pulse-triggered flip-flops comprise the pipeline memory classes considered in this paper. TPDICE basic cells are utilized to achieve fault-tolerance and transient bypass capability. A number of single-ended and differential structures are presented and evaluated with respect to performance, energy consumption, and complexity. In addition, the SEU and SET tolerance of these structures is demonstrated. All evaluations are based off simulations performed in 90 nm CMOS. Accompanying the above evaluations, this paper also addresses concerns of multiple bit upset (MBU) affecting these designs at the 90 nm technology node. Novel hardened-by-design techniques are introduced to address these concerns, and their effectiveness is quantified.