DocumentCode
1078715
Title
Economic approach to fault-tolerant synchronisation
Author
Infis, A.H. ; Moore, W.R.
Author_Institution
Dept. of Electron. & Inf. Eng., Southampton Univ., UK
Volume
135
Issue
2
fYear
1988
fDate
3/1/1988 12:00:00 AM
Firstpage
82
Lastpage
86
Abstract
Previous solutions to the problem of synchronising fault-tolerant multiprocessor systems require either 3t+1 processors (for t-fault-tolerance) or else multiple rounds of messages with unforgeable digital signatures. These solutions are too expensive for small microprocessor-style control systems. The paper shows that simple constraints on the physical design of the communication links permit a much more economical solution with just 2t+1 processors and one round of messages, without the need for unforgeable signatures.
Keywords
fault tolerant computing; multiprocessing systems; synchronisation; digital signatures; fault-tolerant synchronisation; microprocessor-style control systems; multiple rounds; multiprocessor systems; physical design;
fLanguage
English
Journal_Title
Computers and Digital Techniques, IEE Proceedings E
Publisher
iet
ISSN
0143-7062
Type
jour
Filename
42805
Link To Document