DocumentCode :
1078836
Title :
Threshold-voltage instability of n-channel MOSFET´s under bias-temperature aging
Author :
Shiono, Noboru ; Hashimoto, Chisato
Author_Institution :
Nippon Telegraph and Telephone Public Corporation, Tokyo, Japan
Volume :
29
Issue :
3
fYear :
1982
fDate :
3/1/1982 12:00:00 AM
Firstpage :
361
Lastpage :
368
Abstract :
New experimental evidence of positive threshold-voltage shift caused by interface state generation under positive bias-temperature (BT) aging is presented. Interface states were estimated for MOSFET\´s using low-frequency (8-Hz) 
measurement, which was carried out by a lock-in technique. Generated acceptor-type interface states are distributed between the midgap and the conduction-band edge in the forbidden gap. Time( 
) and temperature( 
) dependence for threshold-voltage shift ( 
) is represented experimentally as 
, where 
. The positive VT shift appears faster for MOSFET\´s fabricated with dry O2 oxides as gate insulator than for those with HCI oxides. It is also shown that the VT shift is always larger than the flat-band voltage shift caused by interface state generation under negative BT aging. Generated interface states are distributed in the entire forbidden gap, differing from the case of positive BT aging.
measurement, which was carried out by a lock-in technique. Generated acceptor-type interface states are distributed between the midgap and the conduction-band edge in the forbidden gap. Time( ) and temperature( ) dependence for threshold-voltage shift ( ) is represented experimentally as , where . The positive VKeywords :
Aging; Channel bank filters; Contamination; Electrodes; Interface states; MOS devices; Silicon; Stability; Temperature; Threshold voltage;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1982.20710
Filename :
1482207
Link To Document :
