• DocumentCode
    1078988
  • Title

    A buried channel/surface channel CMOS IC isolated by an implanted silicon dioxide layer

  • Author

    Sano, Eiichi ; Ohwada, Kuniki ; Kimura, Tadakatsu

  • Author_Institution
    Nippon Telegraph and Telephone Public Corporation, Tokyo, Japan
  • Volume
    29
  • Issue
    3
  • fYear
    1982
  • fDate
    3/1/1982 12:00:00 AM
  • Firstpage
    459
  • Lastpage
    461
  • Abstract
    The design and experimental results for a buried channel/ surface channel CMOS IC isolated by an implanted silicon dioxide layer are presented. A Poisson equation is used in proposing a threshold voltage model for a FET with metal-insulator-semiconductor-insulator-semiconductor (MISIS) structure. Good agreement between measured and calculated threshold voltage versus substrate voltage characteristics is obtained. The propagation delay for an inverter is 0.83 ns, which agrees with that from simulation.
  • Keywords
    CMOS integrated circuits; FETs; Impurities; MOSFET circuits; Metal-insulator structures; Poisson equations; Semiconductor device modeling; Silicon compounds; Substrates; Threshold voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1982.20723
  • Filename
    1482220
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1078988