Direct moat isolation for VLSI

Device isolation is a major factor in determining the circuit packing density in VLSI. The scalability of device isolation by local oxidation of silicon (LOCOS) is limited by the large encroachment, including both physical and electrical, into the active device area resulting from lateral oxidation (bird´s beaking) at the edge of isolation oxide and channel stop diffusion into the active device region. An alternative isolation technique is to form the active device area by patterning a thick field oxide uniformly grown or deposited on the silicon substrate. Such a direct moat isolation scheme makes more efficient use of the silicon area by reducing encroachment considerably and thus allowing closer packing of active devices than the LOCOS approach. Direct moat isolation process approaches for VLSI design rules are discussed. Short-channel effects on the subthreshold characteristics of the parasitic devices are studied using a two-dimensional model and compared with experimental measurements. Good device isolation is demonstrated in a parasitic device with a field oxide thickness of 550 nm and a minimum moat-to-moat spacing of 2 µm.