Title :
Systolic architecture for finite field exponentiation
Author :
Ghafoor, A. ; Singh, A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
fDate :
11/1/1989 12:00:00 AM
Abstract :
A systolic pipeline architecture which can perform exponentiation function in a concurrent environment is presented. This function is computed in Galois fields. Under a steady-state condition the throughput of the architecture is shown to be the maximum, with the results appearing at every clock cycle. Being systolic in nature, the architecture is amenable to easy implementation in VLSI.
Keywords :
function evaluation; parallel architectures; pipeline processing; special purpose computers; Galois fields; concurrent environment; exponentiation function; finite field exponentiation; special purpose parallel processor; steady-state condition; systolic pipeline architecture; throughput;
Journal_Title :
Computers and Digital Techniques, IEE Proceedings E
