Title :
A 60 GHz 19.6 dBm Power Amplifier With 18.3% PAE in 40 nm CMOS
Author :
Chien-Wei Tseng ; Yu-Jiu Wang
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
This letter reports a fully integrated 60 GHz power amplifier (PA) implemented in TSMC 40 nm CMOS technology. This PA is based on a three-stage two-way differential topology with an output transformer-based power combining network. This topology improves layout symmetry and mitigates parasitic effects between different signal paths to increase overall efficiency. The use of parasitic coupling capacitors inside a vertically-coupled transformer can increase impedance transformation ratio. This PA achieves 20.3 dB power gain, 19.6 dBm output power with 18.3% peak PAE, and 12 GHz bandwidth.
Keywords :
CMOS analogue integrated circuits; differential amplifiers; field effect MIMIC; millimetre wave power amplifiers; power combiners; transformers; PA; TSMC CMOS technology; bandwidth 12 GHz; efficiency 18.3 percent; frequency 60 GHz; fully integrated power amplifier; gain 20.3 dB; impedance transformation ratio; layout symmetry; output transformer-based power combining network; parasitic coupling capacitors; parasitic effects; signal paths; size 40 nm; three-stage two-way differential topology; vertically-coupled transformer; CMOS integrated circuits; Circuit faults; Impedance; Power generation; Semiconductor device measurement; Transmission line measurements; Voltage measurement; Class-A; cMOS technology; power amplifier (PA); power combining;
Journal_Title :
Microwave and Wireless Components Letters, IEEE
DOI :
10.1109/LMWC.2014.2382682
