Reconfigurable testable bit-serial multiplier for DSP applications

A new testable and reconfigurable bit-serial multiplier is proposed. Fault tolerance is established through built-in self-testing and dynamic reconfiguration. During the reconfiguration phase, the faulty modules of the multiplier are automatically isolated and the system reconfigures itself for the required function with no need for external interference. Quadrupole-double modular redundancy (QDMR) techniques are employed to allow the isolation of the bad modules and the use of only good ones. The faulty cells are located and the diagnostic information is scanned out for evaluation. The followed design method supports a two-level testing strategy, in which the multiplier is tested by a small built-in test circuit and the test circuit itself is tested externally by a scan-path technique, providing high fault coverage. This design method adopts the functional building block concept and is especially suitable for linear arrays. The multiplier is based on the bit-serial approach, which has been proven to be an efficient implementation for several digital-signal-processing (DSP) structures; it accepts 2 s complement data and coefficients in a serial form. A prototype of an 8-bit multiplier has been implemented in single-layer metal 2 mu m CMOS technology; it has an area of 2.64 mm*1.91 mm (without I/O pads) and contains approximately 2500 devices.