Nanosecond NMOS VLSI current mode logic

Current mode logic (CML) is used to obtain NMOS VLSI logic gates with nanosecond delays at a speed power product of 1.5 pJ. The gates use a reference voltage generated by the difference between an enhancement- and a depletion-type MOSFET. A depletion-type MOSFET is used for the current sources and the loads. The gates have been designed with a logic swing of 2 V in a 2.5-µm NMOS VLSI technology, simulated, and their circuit performance is studied.