Memory bandwidth analysis of hierarchical multiprocessors using model decomposition and steady-state flow analysis

For memory bandwidth analysis, researchers generally discard requests that are not accepted during a memory cycle. This assumption simplifies the analysis and produces negligible discrepancies with actual results for a system with a non-hierarchical interconnection network. However, the assumption, “the requests that are not occupied during a memory cycle are discarded,” cannot be used for a multiprocessor system with a hierarchical interconnection network (HIN), because the error introduced assumption can be several orders of magnitude higher than the actual bandwidth. An improved analytical model to determine the bandwidth of a HIN-based system is presented