• DocumentCode
    1080591
  • Title

    Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis

  • Author

    Park, Sun-Mi ; Chang, Ku-Young ; Hong, Dowon

  • Author_Institution
    Dept. of Math., Korea Univ., Seoul
  • Volume
    55
  • Issue
    9
  • fYear
    2006
  • Firstpage
    1211
  • Lastpage
    1215
  • Abstract
    In this paper, we present a bit-parallel multiplier for GF(2m ) defined by an irreducible pentanomial xm+xk 3 +xk 2+xk 1+1, where 1lesk 1 lesk2 lesk3 lesm/2. In order to design an efficient, bit-parallel multiplier, we introduce a shifted polynomial basis and modify a reduction matrix presented by Reyhani-Masoleh and Hasan. As a result, the time complexity of the proposed multiplier is TA+(3+[log2(m-1)])TX , where TA and TX are the delay of one AND and one XOR gate, respectively. This result matches or outperforms the previously known results. On the other hand, the proposed multiplier has the same space complexity as the previously known multipliers except for special types of irreducible pentanomials. Note that its hardware architecture is similar to that presented by Reyhani-Masoleh and Hasan
  • Keywords
    Galois fields; circuit complexity; logic gates; matrix algebra; multiplying circuits; polynomials; AND gate; XOR gate; bit-parallel multiplier; irreducible pentanomials; matrix reduction; shifted polynomial basis; space complexity; Codes; Computer architecture; Delay effects; Digital arithmetic; Elliptic curve cryptography; Galois fields; Hardware; Niobium; Polynomials; Public key cryptography; Bit-parallel multiplier; finite field arithmetic; irreducible pentanomial.; shifted polynomial basis;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2006.146
  • Filename
    1668049