Design of algorithm-based fault-tolerant VLSI array processor

A systematic design methodology which maps a matrix arithmetic algorithm to a fault-tolerant array processor with different topologies and dimensions is presented. The design issues to be addressed in the method are: (a) how to derive a VLSI array with different topologies and dimensions from the algorithm; (b) how to distribute the data processing to the PEs so that a faulty PE will result in limited erroneous data on which the checking scheme is valid. Two examples, matrix multiplication and Givens reduction, are used to illustrate this design method.