A CMOS/SOS gate array with a new customization technique of cutting

A 770-gate single-level metallized Si-gate CMOS/SOS gate array has been fabricated using a new customization technique: cutting pre-defined n⁺epitaxial silicon lines. Simple process and quick turnaround time are both realized. Total fabrication steps are reduced to 53 percent of those of the double-level metallized CMOS/bulk gate array because of a simplified CMOS/SOS process and only three-mask customization. Customization steps are also reduced to 55 percent. High packing density and high switching speed comparable to those of the double-level metallized CMOS/bulk gate array are also obtained. The number of the silicon wiring channels of the conventional single-level metallized gate array is reduced by a factor of two by the cutting technique. This value corresponds to a 24 percent decrease in the chip area. Even with a conservative 4-µm technology, gate delay of 0.8 ns is obtained at the power-supply voltage VDDof 5 V. Up to 25 MHz operations are verified for a shift register. On this gate array a control unit for a CCD camera is fabricated; 95 percent of the internal basic cells are utilized. The active power dissipation of this unit is 1.0 mW at VDDof 5 V.