Design of synchronisers: a review

The synchronisation of asynchronous inputs and metastability in synchronisers have haunted designers of digital systems for a long time. Even though the metastable behaviour of latches and other similar devices is now well understood, it is still a major limitation in digital systems which involve frequent asynchronous interaction. The problem has been studied both theoretically and practically and it has been established that perfect synchronisation is impossible. There are basically two approaches to cope with synchronisation: the first involves special design methodologies, such as self-timed systems, and special components such as stoppable clocks; unfortunately, in many systems, a fixed clock period is required. Alternatively, another technique which involves a well designed synchroniser can be used. The synchronisation problem has been studied by many researchers, in various perspectives. The objective of the paper is to review the problem and put the pieces of the puzzle together; the authors present a simple but complete description of the problem and bridge the gap between circuit designers and system designers.