DocumentCode
1081059
Title
Barrier lowering in short-channel CCD´s
Author
Chen, John Y. ; Viswanathan, C.R.
Author_Institution
Hughes Research Laboratories, Malibu, CA
Volume
29
Issue
10
fYear
1982
fDate
10/1/1982 12:00:00 AM
Firstpage
1588
Lastpage
1593
Abstract
In a two-phase overlapping CCD structure, the potential barrier height in the gap between the two storage gates decreases as the gap length is reduced due to fringing field effects. The barrier lowering limits the charge handling capacity in short-channel CCD´s. A two-dimensional model is developed to calculate the barrier height for the various gap lengths. A simple measurement technique is developed to obtain experimental data using submicrometer structures and the data is compared with the model. Several important process parameters relating to the barrier lowering are investigated for design consideration.
Keywords
Charge coupled devices; Clocks; Computational modeling; Computer simulation; Helium; Interface states; Measurement techniques; Semiconductor process modeling; Very large scale integration; Voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1982.20918
Filename
1482415
Link To Document