• DocumentCode
    1081243
  • Title

    Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs

  • Author

    Xu, Jiang ; Wolf, Wayne ; Zhang, Wei

  • Author_Institution
    Hong Kong Univ. of Sci. & Technol., Hong Kong
  • Volume
    29
  • Issue
    3
  • fYear
    2009
  • Firstpage
    20
  • Lastpage
    30
  • Abstract
    DWP, a new interconnect structure for asynchronous networks on chip in multiprocessing SoCs, yields higher throughput, consumes less power, suffers less from crosstalk noise, and requires less area than traditional interconnect structures. Its advantages stem from techniques including wave pipelining, double-data-rate transmission, interleaved lines, misaligned repeaters, and clock gating.
  • Keywords
    asynchronous circuits; multiprocessor interconnection networks; network-on-chip; pipeline processing; asynchronous NoC; clock gating; double-data-rate transmission; interleaved line; misaligned repeater; multiprocessing SoC; network-on-chip; wave-pipelined interconnect structure; Clocks; Crosstalk; Delay; Network-on-a-chip; Pipeline processing; Repeaters; Size control; Throughput; Transistors; Transmitters; asynchronous; double data rate; interconnect; low power; multiprocessor; network on chip; system on chip; wave pipeline;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2009.40
  • Filename
    5076436
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1081243