A concurrent error detection IC in 2-μm static CMOS logic

Author

Lo, Jien-Chung ; Sun, Shih-Yao ; Daly, James C.

Author_Institution

Dept. of Electr. Eng., Rhode Island Univ., Kingston, RI, USA

Volume

29

Issue

5

fYear

1994

fDate

5/1/1994 12:00:00 AM

Firstpage

580

Lastpage

584

Abstract

When a comprehensive fault model is considered, static CMOS VLSI has long been prohibited from realizing concurrent error detecting (CED) circuits due to the unique analog faults (bridging and stuck-on faults). In this paper, we present the design, fabrication and testing of an experimental chip containing the integration of a totally self-checking (TSC) Berger code checker and a strongly code disjoint (SCD) built-in current sensor (BICS). This chip was fabricated by MOSIS using 2 μm p-well CMOS technology. In chip tests, all implanted faults, including analog faults, were detected as expected. We also show that the self-exercising mechanism of the SCD BICS is indeed functioning properly. This is the first demonstration of a working static CMOS CED chip

Keywords

CMOS integrated circuits; VLSI; built-in self test; error detection; integrated circuit testing; integrated logic circuits; logic testing; 2 micron; Berger code checker; CMOS VLSI; MOSIS; TSC; analog faults; built-in current sensor; concurrent error detection IC; fabrication; fault model; p-well CMOS technology; self-exercising mechanism; static CMOS logic; strongly code disjoint; testing; totally self-checking; CMOS analog integrated circuits; CMOS integrated circuits; CMOS logic circuits; CMOS technology; Circuit faults; Electrical fault detection; Fabrication; Fault detection; Semiconductor device modeling; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.284710

Filename

284710