Working Principles of a DRAM Cell Based on Gated-Thyristor Bistability

This letter discusses the working principles of a memory cell exploiting the bistability of a single nanoscale gated-thyristor to achieve high-performance DRAM operation (T-RAM cell). The device relies on the possibility to reach either of the two stable states of the thyristor by means of a fast low-to-high gate switch and depending on the amount of holes in the gated p-base. In particular, with proper selection of the low and high gate levels, the stationary hole concentration in the p-base leads the thyristor to its high current state while hole depletion results in an orders-of-magnitude lower anode current. This opens the possibility for a DRAM technology with a simple back-end process and fast WRITE and READ operations with low voltage requirements.