Simulating IC reliability with emphasis on process-flaw related early failures

A Monte-Carlo reliability simulator for integrated circuits (IC) that incorporates the effects of process flaws, material properties, the mask layout, and use conditions is presented. The mask layout is decomposed into distinct objects, such as contiguous metal runs, vias, contacts, and gate-oxides, for which user-defined distributions are used for determining the failure probability. These distributions are represented by a mixture of defect-related and wearout-related distributions. The failure distributions for nets (sets of interconnected layout objects) are obtained by combining the distributions of their component objects. System reliability is obtained by applying control variate sampling to the logic network which is comprised of all nets. The effects of k-out-of-n substructures within the reliability network are accounted for. The methodology is illustrated by the effect of particulate-induced defects on metal runs and vias in a simple test circuit. The results qualitatively verify the methodology and show that predictions which incorporate failures due to process flaws are appreciably more pessimistic than those obtained from current practice