A Wide-Range Mixed-Mode DLL for a Combination 512 Mb 2.0 Gb/s/pin GDDR3 and 2.5 Gb/s/pin GDDR4 SDRAM

Author

Lin, Feng ; Royer, Roman A. ; Johnson, Brian ; Keeth, Brent

Author_Institution

Micron Technol., Boise

Volume

43

Issue

3

fYear

2008

fDate

3/1/2008 12:00:00 AM

Firstpage

631

Lastpage

641

Abstract

A mixed-mode delay-locked loop (MDLL) for a 512 Mb graphics SDRAM is presented in this paper. The MDLL extends its lock range into the gigahertz realm by applying clock division and analog phase generation (APG). The divided clock from the MDLL is used for clocking logic and tracking deterministic access latency in the SDRAM. A short discussion of some of the side effects and advantages of using a divided, multi-phase clock for logic operation is presented. A low-power clock distribution network (CDN) based on the presented MDLL is also disclosed. Fabricated in a 1.5 V 95 nm triple-metal CMOS process, the MDLL achieves a measured RMS jitter of 4.6 ps and peak-to-peak jitter of 38 ps at GDDR4 mode with a 1 GHz clock. Power consumption for the entire MDLL-based CDN is 107 mW at 800 MHz and 1.5 V.

Keywords

CMOS integrated circuits; DRAM chips; clocks; delay lock loops; mixed analogue-digital integrated circuits; SDRAM; analog phase generation; clock distribution network; clock division; clocking logic; deterministic access latency; frequency 1 GHz; frequency 800 MHz; mixed-mode delay-locked loop; multiphase clock; power 107 mW; size 95 nm; time 38 ps; time 4.6 ps; triple-metal CMOS process; voltage 1.5 V; wide-range mixed-mode DLL; Circuits; Clocks; Delay; Energy consumption; Frequency synchronization; Jitter; Random access memory; SDRAM; Timing; Voltage; Delay-locked loops (DLL); analog phase generation (APG); clock distribution network (CDN); de-skewing; duty-cycle correction (DCC); synchronous DRAM (SDRAM);

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2007.916623

Filename

4456782