Title :
VA-6 two-dimensional simulation of latch-up in CMOS structure
Author :
Hu, G.J. ; Pinto, M.R. ; Kordic, S.
fDate :
10/1/1982 12:00:00 AM
Keywords :
Analytical models; CMOS process; CMOS technology; FETs; Numerical analysis; Numerical simulation; Semiconductor device modeling; Substrates; Transient analysis; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1982.20988
