• DocumentCode
    1081849
  • Title

    New bit-serial systolic multiplier for GF(2m) using irreducible trinomials

  • Author

    Diab, M. ; Poli, Alessandro

  • Author_Institution
    Univ. Paul Sabatier, Toulouse, France
  • Volume
    27
  • Issue
    13
  • fYear
    1991
  • fDate
    6/20/1991 12:00:00 AM
  • Firstpage
    1183
  • Lastpage
    1184
  • Abstract
    A bit-serial systolic architecture is presented for the product-sum computation P=AB+C in a finite filed GF(2m)=GF(2)(x)/(F(x)), such that F(x)=xm+x+1 is an irreducible trinomial over GF(2). It has a low complexity and does not require connections for the serial transfer of F(x).
  • Keywords
    digital arithmetic; logic circuits; multiplying circuits; systolic arrays; binary RS codes; bit-serial systolic architecture; decoder; encoder; irreducible trinomials; low complexity; product-sum computation; systolic multiplier;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19910738
  • Filename
    132740
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1081849