GaAs LSI-directed MESFET´s with self-aligned implantation for n+-layer technology (SAINT)

Self-aligned implantation for n⁺-layer technology (SAINT) has been developed for improvement in normally-off GaAs MESFET\´s to be used in LSI\´s. This technology has made it possible to arbitrarily control the spacing between the n⁺-implanted layer and gate contact by a dielectric lift-off process utilizing a multilayer resist with an undercut wall shape. SAINT FET\´s with a 1-µm gate length have above 200 mS/ mm transconductance in the normally-off region. The K value along the square-law fitting has been improved by a factor of 3.4, compared to conventional FET\´s without the n⁺-layer. Thermal emission for carriers from the source n⁺-layer in the subthreshold region has been experimentally formulated. Threshold-voltage shift due to gate shortening for [011] gate FET\´s is definitely smaller than that for [011] gate FET\´s. The threshold-voltage standard deviations for [011] gate FET\´s with 2- and 1-µm gate lengths, obtained from a 6-mm × 9-mm area, are 9 and 34 mV, respectively. An E/D direct-coupled FET logics (DCFL) 15-stage ring oscillator with a 1-µm gate length shows a high switching speed of 45 ps/gate at a low supply voltage of 0.91 V.